1. Field
Embodiments of the present disclosure relate to a memory network and a system including the same, and more particularly, to a memory network that is capable of increasing expandability while maintaining substantially the same performance as a conventional memory network, and a system including the same.
2. Description of the Related Art
Recently, memory networks that connect memory devices having router functions, such as hybrid memory cubes (HMCs), have been developed.
A memory network may connect a plurality of central processing units (CPUs) or graphic processing units (GPUs). The memory network and the CPUs or GPUs connected by the memory network may provide a system.
FIG. 1 is a structure diagram of a system including a conventional memory network 10.
The conventional memory network 10 has a dFBFLY (distributor-based Flattened Butterfly) structure.
Hereafter, the term “conventional memory network” refers to a memory network having a dFBFLY structure, and the term “conventional system” refers to a system in which a processor is connected to a memory network having the dFBFLY structure.
In FIG. 1, arrows represent memory channels 2 and processor channels 3. The memory channels 2 are formed between memory devices 11, and the processor channels 3 are each formed between a memory device 11 and a processor 1.
The conventional memory network 10 includes a plurality of memory devices 11 arranged in a grid pattern that includes rows and columns. Each memory device 11 is connected to other memory devices 11 in the same column or the same row by the memory channels 2.
In the conventional system, each of four processors 1 is directly connected to the memory devices 11 included in a corresponding one of four columns by the processor channels 3. The processor 1 may not be directly connected to memory devices 11 in other columns. The processor 1 may be a CPU or GPU.
Since the conventional memory network 10 has higher connectivity than other memory networks known in the art, the conventional memory network 10 provides relatively high performance. However, the conventional memory network 10 has low expandability.
Thus, there is a demand for a new memory network structure with greater expandability and greater or equal performance to the conventional memory network 10.